Hi,

I'm trying to understand the MMU operations & am wondering where is
the kernel code where the kernel interfaces with the this piece of
hardware?

Can some one help me in understanding that what all are the
responsibilities of the kernel, and what is it the hardware takes care
of automatically? E.g. who fills, flushes & refills the TLB entries?
What all initializations need to be performed by kernel (And where is
the code?)

TIA,

Rick
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> E.g. who fills, flushes & refills the TLB entries?
TLB entries are filled by H/W and not explicitly by kernel. Whenever MMU
translates VA to PA it caches that translation into TLB. If TLB is full then
MMU uses its own algorithms to replace some entry in TLB e.g. MMU might
consider TLB as circular buffer and replace first entry once TLB is full.

>What all initializations need to be performed by kernel (And where is
>the code?)
Kernel bascially has to set up the page tables and set the Page Table Base
register and enbale MMU.

Regards
- A.

On 2/5/08, Rick Brown <rick.brown.3 [at] gmail.com> wrote:
>
> Hi,
>
> I'm trying to understand the MMU operations & am wondering where is
> the kernel code where the kernel interfaces with the this piece of
> hardware?
>
> Can some one help me in understanding that what all are the
> responsibilities of the kernel, and what is it the hardware takes care
> of automatically? E.g. who fills, flushes & refills the TLB entries?
> What all initializations need to be performed by kernel (And where is
> the code?)
>
> TIA,
>
> Rick
>
> --
> To unsubscribe from this list: send an email with
> "unsubscribe kernelnewbies" to ecartis [at] nl.linux.org
> Please read the FAQ at http://kernelnewbies.org/FAQ
>
>

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<div>> E.g. who fills, flushes & refills the TLB entries?</div>
<div>TLB entries are filled by H/W and not explicitly by kernel. Whenever MMU translates VA to PA it caches that translation into TLB. If TLB is full then MMU uses its own algorithms to replace some entry in TLB e.g. MMU might consider TLB as circular buffer and replace first entry once TLB is full.</div>

<div><br>>What all initializations need to be performed by kernel (And where is<br>>the code?)</div>
<div>Kernel bascially has to set up the page tables and set the Page Table Base register and enbale MMU.</div>
<div> </div>
<div>Regards</div>
<div>- A.<br> </div>
<div><span class="gmail_quote">On 2/5/08, <b class="gmail_sendername">Rick Brown</b> <rick.brown.3 [at] gmail.com> wrote:</span>
<blockquote class="gmail_quote" style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid">Hi,<br><br>I'm trying to understand the MMU operations & am wondering where is<br>the kernel code where the kernel interfaces with the this piece of<br>
hardware?<br><br>Can some one help me in understanding that what all are the<br>responsibilities of the kernel, and what is it the hardware takes care<br>of automatically? E.g. who fills, flushes & refills the TLB entries?<br>
What all initializations need to be performed by kernel (And where is<br>the code?)<br><br>TIA,<br><br>Rick<br><br>--<br>To unsubscribe from this list: send an email with<br>"unsubscribe kernelnewbies" to ecartis [at] nl.linux.org<br>
Please read the FAQ at http://kernelnewbies.org/FAQ<br><br></blockquote></div><br>

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Hi...

On 2/5/08, sahlot arvind <asahlot [at] gmail.com> wrote:

> TLB entries are filled by H/W and not explicitly by kernel. Whenever MMU
> translates VA to PA it caches that translation into TLB. If TLB is full then
> MMU uses its own algorithms to replace some entry in TLB e.g. MMU might
> consider TLB as circular buffer and replace first entry once TLB is full.

AFAIK, by using certain instructions...you can manually insert
entry/entries to TLB. Same thing to deleting TLB entries. This kind of
technique is used for example on security related software such as
PaX/grsecurity

regards,

Mulyadi.
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>AFAIK, by using certain instructions...you can manually insert
>entry/entries to TLB. Same thing to deleting TLB entries.

Yes you can insert/delete entries in TLB manually. Though I am not sure but
AFAIK, linux kernel does do this.
Please correct if I am wrong.

Regards


On 2/5/08, Mulyadi Santosa <mulyadi.santosa [at] gmail.com> wrote:
>
> Hi...
>
> On 2/5/08, sahlot arvind <asahlot [at] gmail.com> wrote:
>
> > TLB entries are filled by H/W and not explicitly by kernel. Whenever MMU
> > translates VA to PA it caches that translation into TLB. If TLB is full
> then
> > MMU uses its own algorithms to replace some entry in TLB e.g. MMU might
> > consider TLB as circular buffer and replace first entry once TLB is
> full.
>
> AFAIK, by using certain instructions...you can manually insert
> entry/entries to TLB. Same thing to deleting TLB entries. This kind of
> technique is used for example on security related software such as
> PaX/grsecurity
>
> regards,
>
> Mulyadi.
>

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<div>>AFAIK, by using certain instructions...you can manually insert<br>>entry/entries to TLB. Same thing to deleting TLB entries.</div>
<div> </div>
<div>Yes you can insert/delete entries in TLB manually. Though I am not sure but AFAIK, linux kernel does do this.</div>
<div>Please correct if I am wrong.</div>
<div> </div>
<div>Regards<br><br> </div>
<div><span class="gmail_quote">On 2/5/08, <b class="gmail_sendername">Mulyadi Santosa</b> <mulyadi.santosa [at] gmail.com> wrote:</span>
<blockquote class="gmail_quote" style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid">Hi...<br><br>On 2/5/08, sahlot arvind <asahlot [at] gmail.com> wrote:<br>
<br>> TLB entries are filled by H/W and not explicitly by kernel. Whenever MMU<br>> translates VA to PA it caches that translation into TLB. If TLB is full then<br>> MMU uses its own algorithms to replace some entry in TLB e.g. MMU might<br>
> consider TLB as circular buffer and replace first entry once TLB is full.<br><br>AFAIK, by using certain instructions...you can manually insert<br>entry/entries to TLB. Same thing to deleting TLB entries. This kind of<br>
technique is used for example on security related software such as<br>PaX/grsecurity<br><br>regards,<br><br>Mulyadi.<br></blockquote></div><br>

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hadling tlb is architecture specific thing, so its better to search
the manuals of corresponding processor to find out appropriate
instructions to manipulate TLB entries.
AFAI can recall INVLPG is used to invalidate specific pte in TLB.

regards,
mahaveer darade

On 2/5/08, sahlot arvind <asahlot [at] gmail.com> wrote:
> >AFAIK, by using certain instructions...you can manually insert
> >entry/entries to TLB. Same thing to deleting TLB entries.
>
> Yes you can insert/delete entries in TLB manually. Though I am not sure but
> AFAIK, linux kernel does do this.
> Please correct if I am wrong.
>
> Regards
>
>
> On 2/5/08, Mulyadi Santosa <mulyadi.santosa [at] gmail.com> wrote:
> >
> > Hi...
> >
> > On 2/5/08, sahlot arvind <asahlot [at] gmail.com> wrote:
> >
> > > TLB entries are filled by H/W and not explicitly by kernel. Whenever MMU
> > > translates VA to PA it caches that translation into TLB. If TLB is full
> > then
> > > MMU uses its own algorithms to replace some entry in TLB e.g. MMU might
> > > consider TLB as circular buffer and replace first entry once TLB is
> > full.
> >
> > AFAIK, by using certain instructions...you can manually insert
> > entry/entries to TLB. Same thing to deleting TLB entries. This kind of
> > technique is used for example on security related software such as
> > PaX/grsecurity
> >
> > regards,
> >
> > Mulyadi.
> >
>


--
---------------------------
Thanks & Regards,
Mahaveer Darade
mah.darade [at] gmail.com
Mobile - 9970365267


--- Dream it , Code it.

---The "silly question" is the first intimation of some totally new development
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I found one header file for x86 that implement the TLB flushing -
include/asm-x86/tlbflush.h (the different implementation are used are
used because of the diff generation of x86:

static inline void __native_flush_tlb(void)
{
write_cr3(read_cr3());
}

(my questions: WHAT IS THE DIFF BETWEEN FLUSH VIA flush_tlb() above
vs flush_tlb_global() below?)

static inline void __native_flush_tlb_global(void)
{
unsigned long cr4 = read_cr4();

/* clear PGE */
write_cr4(cr4 & ~X86_CR4_PGE);
/* write old PGE again and flush TLBs */
write_cr4(cr4);
}

(question: what is this single - does it flush only ONE SINGLE ENTRY
IN THE TLB that map this particular addr value?)

static inline void __native_flush_tlb_single(unsigned long addr)
{
__asm__ __volatile__("invlpg (%0)" ::"r" (addr) : "memory");
}
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On Feb 6, 2008 7:54 PM, Peter Teoh <htmldeveloper [at] gmail.com> wrote:

> I found one header file for x86 that implement the TLB flushing -
> include/asm-x86/tlbflush.h (the different implementation are used are
> used because of the diff generation of x86:
>
> static inline void __native_flush_tlb(void)
> {
> write_cr3(read_cr3());
> }
>
> (my questions: WHAT IS THE DIFF BETWEEN FLUSH VIA flush_tlb() above
> vs flush_tlb_global() below?)



below function is used to handle tlb entires of global pages as they do not
get flushed from TLB on task switch or writing to cr3


>
> static inline void __native_flush_tlb_global(void)
> {
> unsigned long cr4 = read_cr4();
>
> /* clear PGE */
> write_cr4(cr4 & ~X86_CR4_PGE);
> /* write old PGE again and flush TLBs */
> write_cr4(cr4);
> }
>
> (question: what is this single - does it flush only ONE SINGLE ENTRY
> IN THE TLB that map this particular addr value?)


yes thats right !! its used to invalidate particular PTE entry in TLB.


>
>
> static inline void __native_flush_tlb_single(unsigned long addr)
> {
> __asm__ __volatile__("invlpg (%0)" ::"r" (addr) : "memory");
> }
>



--
---------------------------
Thanks & Regards,
Mahaveer Darade
mah.darade [at] gmail.com
Mobile - 9970365267


--- Dream it , Code it.

---The "silly question" is the first intimation of some totally new
development

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<br><br><div class="gmail_quote">On Feb 6, 2008 7:54 PM, Peter Teoh <htmldeveloper [at] gmail.com> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
I found one header file for x86 that implement the TLB flushing -<br>include/asm-x86/tlbflush.h (the different implementation are used are<br>used because of the diff generation of x86:<br><br>static inline void __native_flush_tlb(void)<br>
{<br>        write_cr3(read_cr3());<br>}<br><br>(my questions:   WHAT IS THE DIFF BETWEEN FLUSH VIA flush_tlb() above<br>vs flush_tlb_global() below?)</blockquote><div><br><br>below function is used to handle tlb entires of global pages as they do not get flushed from TLB on task switch or writing to cr3<br>
<br></div><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"><br><br>static inline void __native_flush_tlb_global(void)<br>{<br>        unsigned long cr4 = read_cr4();<br>
<br>        /* clear PGE */<br>        write_cr4(cr4 & ~X86_CR4_PGE);<br>        /* write old PGE again and flush TLBs */<br>        write_cr4(cr4);<br>}<br><br>(question:   what is this single - does it flush only ONE SINGLE ENTRY<br>
IN THE TLB that map this particular addr value?)</blockquote><div><br>yes thats right !! its used to invalidate particular PTE entry in TLB.<br> </div><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<br><br>static inline void __native_flush_tlb_single(unsigned long addr)<br>{<br>        __asm__ __volatile__("invlpg (%0)" ::"r" (addr) : "memory");<br>}<br></blockquote></div><br><br clear="all">
<br>-- <br>---------------------------<br>Thanks & Regards,<br>Mahaveer Darade<br>mah.darade [at] gmail.com<br>Mobile - 9970365267<br><br><br>--- Dream it , Code it.<br><br>---The "silly question" is the first intimation of some totally new development

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